synthesis techniques and optimization for reconfigurable systems discusses methods used to model reconfigurable applications at the system level, many of which could be incorporated directly into modern compilers. the book also discusses a framework for reconfigurable system synthesis, which bridges the gap between application-level compiler analysis and high-level device synthesis. the development of this framework (discussed in chapter 5), and the creation of application analysis which further optimize its output (discussed in chapters 7, 8, and 9), represent over four years of rigorous investigation within uclas embedded and reconfigurable laboratory (erlab) and ucsbs extensible, programmable and reconfigirable embedded systems (express) group. the research of these systems has not yet matured, and we continually strive to develop data and methods, which will extend the collective understanding of reconfigurable system synthesis. synthesis techniques and optimization for reconfigurable systems assumes a basic understanding of logic design, hardware synthesis (from high-level architecture generation down to placement and routing), and the structure and form of high-level application constructs (such as loops and branches). however, this book may be read and used in the absence of such background knowledge. this text is aimed at researchers and system-level designers (both academic and industrial), but could easily be used as the text of graduate-level course on reconfigurable system synthesis techniques.