Name: Multicore Hardware-Software Design and Verification Techniques (en Inglés)
Price: 83480.00 CLP
Availability: InStock
Author: Chen, Yean Ru ; Lin, Chao Sheng ; Hsiung, Pao Ann
ISBN: 9781608056859

portada Multicore Hardware-Software Design and Verification Techniques (en Inglés)

Formato

Libro Físico

Autor

Pao Ann Hsiung

Editorial

Bentham Science Publishers

Idioma

Inglés

N° páginas

106

Encuadernación

Tapa Blanda

Dimensiones

27.9 x 21.6 x 0.7 cm

Peso

0.36 kg.

ISBN13

9781608056859

Categorías

Arquitectura y diseño lógico de ordenadores

Multicore Hardware-Software Design and Verification Techniques (en Inglés)

Pao Ann Hsiung (Autor) · Bentham Science Publishers · Tapa Blanda

Libro Físico

$ 83.480

$ 151.780

Ahorras: $ 68.300

45% descuento

Envío normal

Origen: Estados Unidos (Costos de importación incluídos en el precio)

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Reseña del libro "Multicore Hardware-Software Design and Verification Techniques (en Inglés)"

The surge of multicore processors coming into the market and on users' desktops has made parallel computing the focus of attention once again. This time, however, it is led by the industry, which ensures that multicore computing is here to stay. Nevertheless, there is still so much research work to be done in multicore hardware-software designs before consumer applications can leverage the benefits of this new paradigm. This book is being put forward as a platform for immediate collection of state-of-the-art technologies in both hardware and software designs for multicore computing. With the burgeoning prevalence of multicore processors in embedded systems, real-time systems, multimedia systems, bioinformatics systems, network systems, to list a few, this book attempts to cover the design and verification issues related to different application domains as a singular source of reference to the state-of-the-art techniques in multicore processor design and software programming that covers multiple application domains. This book will be of immense help to system and software engineers, including both experts and non-experts in parallel computing.