Compartir
Direct Transistor-Level Layout for Digital Blocks (en Inglés)
Rob A. Rutenbar
(Autor)
·
Prakash Gopalakrishnan
(Autor)
·
Springer
· Tapa Blanda
Direct Transistor-Level Layout for Digital Blocks (en Inglés) - Gopalakrishnan, Prakash ; Rutenbar, Rob A.
Libro Nuevo
Importado
Envío: 13 a 18 días háb.
$ 199.140$ 99.570
Costos de importación incluídos en el precio ✅
Reseña del libro "Direct Transistor-Level Layout for Digital Blocks (en Inglés)"
Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library. Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability. The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
- 0% (0)
Todos los libros de nuestro catálogo son Originales.
El libro está escrito en Inglés.
La encuadernación de esta edición es Tapa Blanda.
✓ Producto agregado correctamente al carro, Ir a Pagar.
